1. Field of the Invention
This invention generally relates to VLSI circuit design and more specifically relates to optical proximity correction in the design of lithographic masks that require coloring, for example, in alternating phase shift masks or double exposure masks.
2. Description of Related Art
Integrated circuits including very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) devices are manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well-defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base (or other) material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending in the removal of the expended photoresist to make way for a new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of a light source, a stencil, or photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. Since a wafer containing from fifty to one hundred chips is patterned in steps of one to four chips at a time, a lithography stepper is limited by parameters described in Rayleigh's equation:
                    R        =                              k            l                    ⁢                                          ⁢                      λ            NA                                              (        1        )            
where λ is the wavelength of the light source used in the projection system and NA is the numerical aperture of the projection optics used. k1 is a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from 0.8 down to 0.5 for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm wavelength. Steppers operating at a wavelength of 356 nm are also in widespread use.
Conventional photomasks consist of chromium patterns on a quartz plate, allowing light to pass wherever the chromium is removed from the mask. Light of a specific wavelength is projected through a mask onto the photoresist coated wafer, exposing the resist wherever holes are patterned on the mask. Exposing the resist to light of appropriate wavelength causes modifications in the molecular structure of the resist polymers which allows a developer chemical to dissolve and remove the resist in the exposed areas. (Conversely, negative resist systems allow only unexposed resist to be developed away.) The photomask, when illuminated, can be pictured as an array of individual, infinitely small light sources, which can be either turned on (points covered by clear areas) or turned off (points covered by chrome).
These conventional photomasks are commonly referred to as chrome on glass (COG) binary masks. The perfectly square step function exists only in the theoretical limit of the exact mask plane. At any distance away from the mask, such as in the wafer plane, diffraction effects will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to λ/NA (NA being the numerical aperture of the exposure system), electric field vectors of nearby images will interact and add constructively. The resulting light intensity curve between features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected light image, that is, the intensity difference between adjacent light and dark features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process latitude; that is the amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process latitude or allows operation of a lower k1 value (see equation 1) by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so in addition to turning the electric field amplitude on and off, the phase of the vector can be changed. This phase variation is achieved in PSM's by modifying the length that a light beam travels through the mask material. By recessing the mask by the appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the mask will be 180° out of phase; that is, their electric field vectors will be of equal magnitude but point in exactly opposite directions so that any interaction between these light beams results in perfect cancellation. For more information on PSM, the reader is referred to “Phase-Shifting Mask: Strategies: Isolated Dark Lines, ” Marc D. Levenson, Microlithography World, March/April 1992, pp. 6-12. The limits of PSM lithography can be uniquely challenged by the manufacture of high-performance logic derivatives of advanced Dynamic Random Access Memory (DRAM) technologies. These technologies are entering development cycles with immediate requirements for sub-quarter micron printed gate lengths and tight dimensional control on the gate structures across large chip areas. Since these logic technologies are based on shrinking the gate length in an established DRAM technology, the overall layout pitch remains constant for all critical mask levels, resulting in narrow, optically isolated lines on the scaled gate level. The requirement for tight line width control on narrow isolated lines drives the requirement of phase edge PSM's for these logic applications. Phase edge PSM lithography makes use of contrast enhancement caused by a phase transition under an opaque feature on a mask. This phase transition is achieved by etching an appropriate depth into the quartz mask substrate on one side of a narrow line structure on the mask. Since the 180° phase transition forces a minimum in the image intensity, narrow dark lines will be printed by these excess phase edges. Currently, the unwanted images are erased using a trim mask, a second mask that transmits light only in regions left unexposed by the residual phase edge.
Even though resolution enhancement through the use of phase shifted masks has been extensively proven, implementation of this technique is critically dependent on computer assisted design (CAD) technology that can modify existing circuit designs to incorporate the additional design levels needed to build a phase shifted mask. Design modifications consist of defining regions on the mask that require phase shifting (i.e., by etching into the mask substrate), and trim regions required to eliminate lines printed by unwanted phase edges, and then inserting additional shapes on the respective design levels (ie: phase, trim). The process of defining portions of the mask as 0° phase transition and other portions as 180° phase transition is generally referred to as phase coloring. The challenge for phase coloring algorithms to find a globally correct solution depends highly on design styles. Thus such algorithms have been difficult to effectively automate.
Currently phase coloring is considered a binary design problem and uses nets and net coloring to form the mask. The method in general assigns binary qualities (such as “−” or “+”) in a way that eliminates conflicts between design elements. In phase-shifted mask designs, portions of the mask are assigned a 0° phase shift and other portions are assigned 180° phase shifts such that the image intensity between the portions is minimized. Thus, the phase shifted mask design is a type of binary problem, one that can be solved using phase coloring.
Phase coloring methods can be adapted to generate phase- shifted mask designs from traditional flat VLSI CAD data or hierarchical VLSI CAD data.
A method for phase coloring for flat databases and hierarchial databases is shown in U.S. Pat. No. 5,883,813 to Kim et al. and which is assigned to the assignee of the present invention. This patent is incorporated herein by reference.
CAD data structures for a VLSI circuit design can include either flat data structures or hierarchical data structures. The CAD data structure inputs include each shape element to be fabricated on a mask, and the location of that shape on the mask. Of course, such a data structure for a VLSI device is extremely complex, and could contain millions of shapes for each mask, with several masks required for each device. Preferably, the data is maintained in hierarchical data structures for minimizing storage and computational resources.
In the generation of phase shift masks, the phase coloring of one shape can affect the phase coloring of a “nearby” shape. Such shapes are “coupled” with respect to phase coloring. Each pair of nearby shapes is referred to as an “intrusion pair,” meaning the phase of one determines the phase of the other. The CAD data structure input preferably contains a list of all intrusion pairs or otherwise contains the data from which the intrusion pair list can be derived.
The method of the Kim patent forms a database of element shapes and their color is assigned. This data base is generally referred to as a net list. A net is a set of shapes that are phase coupled together and are treated as a single entity, with the phase coupling as the “connected” function that allows the shapes to be stored as a net. Nets that are elements of higher level nets are referred to as “nested nets”.
The method continues until all intrusion pairs have been located and assigned a color and a net. Those shapes that are not nearby any other shape can be arbitrarily assigned either color unless otherwise constrained.
In addition to working with flat VLSI CAD data structures, the Kim et al. patent can be applied to hierarchical VLSI CAD data structures. Many CAD systems describe the physical design of VLSI devices in the form of hierarchical 2-dimensional geometric models. These systems simplify the complex task of designing VLSI devices, but have traditionally had problems analyzing the hierarchical design. The primary reason for this is that traditional methods have analyzed the data flat, (i.e., all instances of mask shapes are transformed into the coordinate system of the root node of the design) whereas mask data is typically designed nested (i.e., the mask shapes are designed hierarchically and may be reused in a design many times). One system and method for creating hierarchical representations of interconnections between VLSI circuit design components to facilitate the analysis of a design while still in its nested form was described by Kim et al. in “System and Method for Building Interconnections in Hierarchical Circuit Design,” U.S. Pat. No. 5,481,473, and assigned to International Business Machines Corp. and incorporated herein by reference. The system uses a form of the graphical technique known as inverse layout trees to describe the interconnections. The inverse layout tree is a forest of trees each rooted at a leaf node of the layout tree. Thus, in a typical implementation, a design mask shape would form the root of an inverse layout tree, while the leaves would represent flat layouts of the rooted mask shape. The use of the inverse layout tree has provided a means for manipulating instances of a mask shape at varying levels of nesting.
This system uses nets to group components of a design that are interconnected by some set of rules. In particular, the system uses nested net synthesis to identify and store the interconnection data between shapes in a nested component design. In particular, the system uses nested net synthesis to identify and store interconnections (such as electric or magnetic interconnections) of VLSI design components of a nested design while maintaining the data in its nested form.
Similarly, nested net synthesis can be used to identify and store phase coupling between mask shapes in a hierarchical VLSI database and the Kim et al. method can operate on this database to appropriately color the mask shapes to minimize the image intensity between them. Groups of locally interacting mask shapes are represented by independent subnets of mask shapes within the layout tree.
Thus, the Kim et al. method automatically colors VLSI design elements for the purpose of assigning binary properties to the elements. The method of Kim et al. attempts to find a clean coloring solution within each of the subnets by traversing the subnet and flipping the color of elements while attempting to find a clean coloring solution without flattening the data. However, as design density increases, subnet sizes increase and the probability of finding a clean coloring solution is significantly diminished, and flattening becomes required.
Adding phase modulation to the photomask can profoundly increase the attainable resolution. Other resolution enhancement methods have also been shown to increase attainable resolution and some of these must also undergo a coloring step similar to alternating phase shift masks. An example of one of these methods is the decomposition of a single patterning layer into two layers that are printed on two masks. The assignment of particular shapes to each decomposed mask is referred to hereinafter as coloring (which is analogous to assigning phase coloring in altPSM technology). Each of the two masks is then exposed on the wafer and their resulting images recombined to form the original desired pattern. If both masks are exposed into a single film of photoresist, this technique is generally referred to as double-exposure (DE), which is widely known in the art. If the first exposure is transferred into a secondary film and then another layer of photoresist added to the wafer and exposed with the second mask, the technique is often called double-exposure-double-etch (DE2) which is also known in the art. Although these patterning techniques are known, they are not widely practiced due to, among other reasons, the difficulty of decomposing a realistic design layout into two mask layers.
Sub-wavelength lithography, where the size of printed features is smaller than the exposure wavelength, places a tremendous burden on the lithographic process. Distortions of the intended images inevitably arise, primarily because of the nonlinearities of the imaging process and the nonlinear response of the photoresist. Two of the most prominent types of distortions are the wide variation in the linewidths of identically drawn features in dense and isolated environments (dense-iso bias) and the line-end pull-back or line-end shortening (LES) from drawn positions. The former type of distortion can cause variations in circuit timing and yield, whereas the latter can lead to poor current tolerances and higher probabilities of electrical failure.
Optical proximity correction or optical proximity compensation (OPC) is the technology used to compensate for these types of distortions. OPC is loosely defined as the procedure of compensating (pro-distorting) the mask layout of the critical IC layers for the lithographic process distortions to follow. This is done with specialized OPC software. In the heart of the OPC software is a mathematical description of the process distortions. This description can either be in the form of simple shape manipulation rules, in which case the OPC is referred to as “rule-based OPC or a more detailed and intricate process model for a “model-based OPC (MBOPC).” The OPC software automatically changes the mask layout by moving segments of line edges and adding extra features that (pre-) compensate the layout for the distortions to come. Although after OPC has been performed the mask layout may be quite different than the original (before OPC) mask, the net result of this procedure is a printed pattern on the wafer that is closest to the IC designer's original intent. There are commercially available software tools that perform OPC on a full-chip scale. OPC relies heavily on speedy calculations of the image intensity at selected points of the image field.
In general, with large densely packed designs, photomasks that require coloring, such as alternating PSM or decomposed masks for DE or DE2, are typically flattened (i.e. to the top level of the hierarchy) in obtaining the coloring solution. Thus, flattened data is passed down to the OPC engine which spends days in processing and is generally ineffective. Therefore, there is a need for a more efficient OPC technology that takes advantage of the hierarchical data structure for densely packed photomask designs that require coloring.